Controlled frequency power factor correction circuit and method

ABSTRACT

A power factor correction (PFC) circuit ( 10 ) includes a latch ( 16 ) having an output that initiates a coil current (I COIL ) in response to a transition edge of a clock signal (CLOCK) to generate a PFC signal (V OUT ). An input receives a control signal (TERM). A current modulation circuit ( 14 ) has a first input ( 36 ) coupled for receiving the PFC signal to establish a charging time (T CH ) of the coil current. A second input senses the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output ( 38 ) provides the control signal as a function of the charging time and the duty cycle.

BACKGROUND OF THE INVENTION

The present invention relates in general to integrated circuits and,more particularly, to integrated power factor correction circuits.

Integrated power factor correction (PFC) circuits are switching circuitsthat ensure that an alternating current (AC) line is loaded with anin-phase, substantially sinusoidal current. Without PFC correction, manyelectrical systems draw current from the AC line voltage only near thepeak voltage levels of the AC line. The aggregate effect of loading theAC line with large currents at the voltage peaks and zero current atother times is to produce distortion of the AC line voltage. Inaddition, systems without PFC can cause high neutral currents to flow inthree-phase distribution networks. To avoid these problems so thatelectrical devices function properly, the distribution networks ofregional utility companies must be oversized, which necessitates a largecapital investment. Several governments are mandating that PFC beincorporated in the power supplies used in some or all electricaldevices.

PFC circuits typically switch current through an inductor or coil fromthe AC line at a frequency much higher than the frequency of the AC lineto magnetize or charge a coil. For example, systems may use a switchingfrequency of at least one hundred kilohertz when the AC line frequencyis fifty hertz. The energy stored in the coil is discharged into acapacitor to generate an intermediate PFC direct current (DC) supplyvoltage to power an electrical device or system. To attain asubstantially sinusoidal AC current, the average value over a switchingperiod of the current switched through the coil is made proportional tothe current voltage on the AC line. The result is a high effective powerfactor for the AC line.

Most previous PFC circuits operate in a free-running mode in which acurrent is switched to charge the coil as soon as the coil currentstored in the previous cycle has been discharged across the capacitor.As a result, the previous PFC circuits switch at a frequency that varieswith the current AC line voltage as well as the system's load current.Such variable switching frequencies are difficult to filter out in orderto suppress or remove electromagnetic interference generated by theswitched coil currents. Such filtering requires complex filters whichdissipate power and substantially increase the manufacturing cost of asystem.

Hence, there is a need for a PFC circuit and method of correcting thepower factor that operates at a fixed or nearly fixed frequency in orderto reduce a system's electromagnetic interference while maintaining alow fabrication cost of the PFC circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a power factor correction (PFC)circuit;

FIG. 2 is a timing diagram showing waveforms of the PFC circuit;

FIG. 3 is a schematic diagram of a duty cycle sensor of the PFC circuit;

FIG. 4 is a schematic diagram of a current modulator of the PFC circuit;and

FIG. 5 is a schematic diagram of the current modulator in an alternateembodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

In the figures, elements having the same reference number have similarfunctionality.

FIG. 1 is a schematic diagram of a power factor correction (PFC) circuit100 controlled by a PFC control circuit 10 and including a diode bridge20, resistors 22-24, an inductor or coil 25, a diode 26, an outputcapacitor 27, a timing capacitor 28 and a switching transistor 29. PFCcircuit 100 receives a sinusoidal voltage VAC from an alternatingcurrent (AC) line and produces a direct current (DC) PFC output signalV_(OUT) at a node or output 30. In one embodiment, PFC circuit 100functions as a step up switching regulator that receives VAC at a valueof about two hundred twenty volts root-mean-square (RMS) and a frequencyof about fifty hertz and produces PFC output voltage V_(OUT) with avalue of about four hundred volts DC. In some regions, VAC has a valueof about one hundred ten volts RMS and V_(OUT) a frequency of sixtyhertz. VAC has a typical range of about plus and minus, twenty percent.

Diode bridge 20 is a standard full-wave bridge rectifier that rectifiesline voltage VAC and produces a rectified sine wave voltage V_(IN) at anode 32 with a frequency of twice the frequency of VAC or about onehundred hertz and a peak value of about three hundred ten volts. Acapacitor (not shown) may be connected across diode bridge 20 to reduceVAC noise peaks.

Coil 25 has a typical inductance L=100.0 microhenries and a lowequivalent series resistance for high efficiency operation.

Transistor 29 is a high current n-channel metal-oxide-semiconductorfield effect transistor that switches a coil current I_(COIL) throughcoil 25. In one embodiment, transistor 29 is a power transistor able toswitch peak values of coil current I_(COIL) greater than two amperes.These currents are small near the zero crossing point of VAC and largenear the VAC voltage peaks. Transistor 29 typically has a large gatecapacitance greater than five hundred picofarads.

Coil current I_(COIL) has a component charging current I_(CH) and acomponent discharging current I_(DSCH). Charging current I_(CH) flowsthrough coil 25 to store magnetic energy in coil 25 when transistor 29is on. When transistor 29 switches off, the stored magnetic energy flowsas discharge current I_(DSCH) from coil 25 through diode 26 to capacitor27 to develop PFC voltage V_(OUT) on node 30.

Coil current I_(COIL) has a return path through resistor 22 to diodebridge 20 which develops a current sense voltage V_(IS) on a node 31 tomonitor when I_(COIL) is flowing. In one embodiment, resistor 22 has aresistance of about 0.2 ohms, so V_(IS) has a value of about −0.2 voltswhen I_(COIL) has a magnitude of one ampere. Alternatively, theconduction time of I_(COIL) can be measured using a voltage sensingtechnique, rather than the current sensing arrangement shown in FIG. 1.For example, coil 25 can be formed as a primary winding of a transformerwhose secondary winding has a terminal coupled at node 31 to the inputof duty cycle sensor 12, typically through a resistor, the othersecondary winding terminal being grounded. The secondary windinggenerates current sense voltage V_(IS) with a positive voltage whenI_(COIL) is charging, a negative voltage while I_(COIL) is discharging,and with substantially zero volts when I_(COIL) is zero.

The magnitude of I_(COIL) is a function of PFC output voltage V_(OUT),and is controlled by feeding back V_(OUT) through a voltage dividerformed with resistors 23 and 24. This voltage divider samples V_(OUT)and provides a sense voltage V_(SENSE) on a node 36. Resistors 23 and 24have resistances of R₂₃ and R₂₄, respectively.

PFC control circuit 10 includes a duty cycle sensor 12, a currentmodulator 14, a flip-flop or latch 16 and an output buffer 18. Currentmodulator 14 produces a timing current I_(TIMING) that charges anexternal capacitor 28 to develop a timing voltage V_(TIMING) thatcontrols the period of charging current I_(CH), and therefore its peakamplitude, as described below. In one embodiment, PFC control circuit 10is formed on a semiconductor substrate as an integrated circuit.

Output buffer 18 is a standard non-inverting amplifier that is capableof driving the high capacitive load presented by transistor 29.

Latch 16 is a standard R-S flip-flop that has a Q output providing adigital switching signal VSW which is set on a transition edge of aclock signal CLOCK and reset on a transition edge of a digitaltermination signal TERM. To achieve a high power factor, CLOCKpreferably operates at a frequency much greater than the frequency ofV_(IN). In one embodiment, V_(IN) has a frequency of about one hundredhertz, or a period of about ten milliseconds, and CLOCK pulses aregenerated at a controlled or substantially constant frequency of aboutone hundred kilohertz, or a period of about ten microseconds. When VSWis set, transistor 29 turns on through output buffer 18 to initiatecharging component I_(CH) of coil current I_(COIL) to magnetize or storeenergy in coil 25. When VSW is reset, transistor 29 is turned offthrough output buffer 18, terminating charging component I_(CH) andinitiating discharging component I_(DSCH) of I_(COIL), which flowsthrough diode 26 to transfer energy from coil 25 to capacitor 27.

Duty cycle sensor 12 monitors coil current I_(COIL). and produces adigital coil current sense signal COILON at an output 34 which is logichigh when I_(COIL) has a substantially nonzero value and logic low whenI_(COIL) is zero. A comparator compares current sense signal V_(IS) witha reference signal V_(REF2) to generate COILON. In one embodiment, dutycycle sensor 12 includes a preamplifier that increases the magnitude ofV_(IS) to improve noise immunity. Since VSW is set on each CLOCK pulseto begin a new cycle, the portion of a CLOCK period in which COILON islogic high is indicative of the duty cycle of I_(COIL).

Current modulator 14 has an input at node 36 that monitors PFC signalV_(OUT) through sense signal V_(SENSE) to establish a time T_(CH) forthe charging portion I_(CH) of coil current T_(COIL). An input at node34 senses when I_(COIL) is flowing to provide a digital signal COILONthat establishes a duty cycle of I_(COIL) over a CLOCK period. Currentmodulator 14 includes an error amplifier that amplifies the differencebetween V_(SENSE) and a reference voltage V_(REF1) to produce acorrection signal V_(ERR) for setting the magnitude of I_(COIL), andtherefore the time T_(CH). This amplification is integrated with COILONover a period of CLOCK to produce termination signal TERM at an outputat node 38 to terminate charging current I_(CH) and initiate dischargingcurrent I_(DSCH). Hence, TERM is produced as a function of T_(CH) andthe duty cycle. In one embodiment, TERM is produced so as to maintain aconstant product of T_(CH) and the duty cycle of I_(COIL)

Switching cycles of PFC control circuit 10 are initiated by clock signalCLOCK which preferably operates at a constant or nearly constantfrequency. Since the period of CLOCK is much smaller than the period ofV_(IN), a substantially constant voltage V_(IN) appears across coil 25when transistor 29 turns on. Coil current I_(COIL) increases linearlywith a slope approximately equal to V_(IN)/L, so its peak value isI_(PEAK)=T_(CH)*V_(IN))/L, where T_(CH) is the duration of chargingcurrent I_(CH). Similarly, the slope of discharging current I_(DSCH) isapproximately equal to (V_(OUT)−V_(IN))/L, and its durationT_(DSCH)=L*I_(PEAK)/(V_(OUT)−V_(IN)). Hence, the total period whenI_(COIL) is nonzero is given by equation 1), $\begin{matrix}{T_{COIL} = {{T_{CH} + T_{DSCH}} = {L \cdot I_{PEAK} \cdot {\frac{V_{OUT}}{V_{IN} \cdot \left( {V_{OUT} - V_{IN}} \right)}.}}}} & \left. 1 \right)\end{matrix}$

It can be shown that the average coil current T_(COIL) _(—) _(CLOCK)over a CLOCK period T_(CLOCK) is given by equation 2), $\begin{matrix}{I_{COIL\_ CLOCK} = {{\frac{V_{IN} \cdot T_{CH}}{2 \cdot L} \cdot \frac{\left( {T_{CH} + T_{DSCH}} \right)}{T_{CLOCK}}} = {\frac{V_{IN}}{2 \cdot L}\left( {T_{CH} \cdot D_{CYCLE}} \right)}}} & \left. 2 \right)\end{matrix}$where D_(CYCLE)=(T_(CH)+T_(DSCH))/T_(CLOCK). A high power factor isachieved when the average coil current I_(COIL) _(—) _(CLOCK) followsthe rectified sinusoidal shape of V_(IN), which occurs ifT_(CH)*D_(CYCLE) is made constant.

The operation of PFC control circuit 10 can be seen by referring to FIG.2, which is a timing diagram showing selected waveforms of PFC controlcircuit 10. Initially, at time T0, assume that clock signal CLOCK,switching signal VSW, termination signal TERM and coil current sensesignal COILON are all low. Further assume that coil current I_(COIL),current sense voltage V_(IS), timing current I_(TIMING) and timingvoltage V_(TIMING) each are equal to zero.

At time T1, a low to high transition edge of CLOCK sets latch 16 toinduce a low to high transition of VSW, turning on transistor 29 throughbuffer 18 to initiate coil current I_(COIL). Note that the component ofI_(COIL) that begins to flow at time T1 is charging current I_(CH).Since the period of CLOCK is much less than the period of V_(IN), andthe voltage drop across transistor 29 typically is small, asubstantially constant voltage V_(IN) is applied across coil 25 to causeI_(COIL) to increase linearly or ramp up at a rate V_(IN)/L as shown.I_(COIL) flows through resistor 22 to develop current sense voltageV_(IS), which also ramps linearly but in a negative voltage direction asshown. The low to high VSW transition sets COILON high to enable timingcurrent I_(TIMING), which charges capacitor 28 to develop timing voltageV_(TIMING) as a linear ramp.

At time T2, V_(TIMING) reaches a threshold voltage to generate a low tohigh transition of termination signal TERM, which resets latch 16. Thisthreshold voltage may be a predetermined voltage or a variable voltage,as described in detail below. A high to low transition of VSW terminatescharging current I_(CH) and initiates discharging current I_(DSCH) ofT_(COIL) to transfer energy from coil 25 to capacitor 27. VSW alsocloses a switch that discharges capacitor 28 and shunts I_(TIMING) toground to reduce V_(TIMING) to zero as shown. I_(DSCH) decreases in alinear fashion with a slope (V_(OUT)−V_(IN))/L until the magnetic energystored in coil 25 is fully discharged.

At time T3, I_(COIL) decreases to zero. Current sense signal V_(IS) alsoramps to zero, which produces a high to low transition of coil currentsense signal COILON. I_(COIL) remains substantially zero for theremainder of the CLOCK period until time T4, when the next cycle begins.

FIG. 3 shows a schematic diagram of duty cycle sensor 12 coupled toresistor 42, including an amplifier 44, a comparator 45, a latch 46 andresistors 42-43. Duty cycle sensor 12 receives sense signal V_(IS) atnode 31 through resistor 42 to monitor the flow of coil currentI_(COIL). An output is coupled to node 34 to produce coil current sensesignal COILON with a logic low value when I_(COIL) is substantially zeroand a logic high value when I_(COIL) is nonzero.

At time T1, a logic low to high transition of clock signal CLOCK setsswitching signal VSW to a logic high value to initiate coil currentI_(COIL). Latch 46 is set to produce a low to high logic transition ofCOILON on node 34 to indicate that I_(COIL) is flowing, i.e., has anonzero value. Concurrently, sense signal V_(IS) ramps from zero to anegative value.

Amplifier 44 and resistors 42-43 function as a gain stage that amplifiesV_(IS) to increase the system noise immunity. In one embodiment,resistor 43 has a value of about ten kilohms and resistor 42 has a valueof about one kilohm, which results in an amplified signal on a node 41whose value is about (−10*V_(IS)). Hence, node 41 ramps from zero to apositive level until time T2, when its value begins to decrease towardzero volts as coil 25 discharges. When the potential on node 41decreases to a value less than V_(REF2), comparator 45 generates a logiclow to high transition of a reset signal V_(R), which resets latch 46 toproduce a high to low logic transition of COILON that indicates thatI_(COIL) has discharged to substantially zero. In practice, V_(REF2) maybe set to a small positive nonzero value to avoid an oscillatorycondition in comparator 45 that effectively introduces noise in V_(R).In one embodiment, V_(REF2) is set to 0.1 volts, which corresponds to avalue of I_(COIL)=0.05 amperes.

FIG. 4 is a schematic diagram showing current modulator 14 in furtherdetail, including amplifiers 47-48, a comparator 49, switches 50-51,resistors 52-53, capacitors 54-55 and a current source 56. Resistors 52and 53 have resistances R₅₂ and R₅₃, respectively, while capacitors 54and 55 have capacitances C₅₄ and C₅₅, respectively.

Amplifier 47 functions as an error amplifier that compares sense signalV_(SENSE) to reference voltage V_(REF1) and amplifies their differenceto produce correction signal V_(ERR) on node 72. In effect, amplifier 47amplifies the difference between the desired value ofV_(OUT)=V_(REF1)*(1+R₂₃/R₂₄) and the actual current value of V_(OUT).PFC control circuit 10 effectively regulates VOUT by maintaining VSENSEsubstantially equal to VREF. Capacitor 54 and resistors 23-24 functionas an integrator or low pass filter which filters out either one hundredhertz or one hundred twenty hertz ripple in V_(SENSE) which may bepresent in PFC signal V_(OUT), depending on the local or regionalfrequency of VAC. Capacitor 54 and resistors 23-24 produce anintegration time constant R₂₃*R₂₄*C₅₄/(R₂₃+R₂₄) that attenuatesV_(SENSE) fluctuations having a shorter duration. In one embodiment, thetime constant is at least five times the period of V_(IN) so, forexample, when V_(IN) has a period of ten milliseconds, the time constantis set to be at least fifty milliseconds. Hence, V_(ERR) is consideredto be substantially constant over a period of V_(IN).

Correction signal V_(ERR) is effectively divided by the duty cycle ofI_(COIL) in a gain stage 70 that includes amplifier 48, resistors 52-53,capacitor 55 and switch 50. Gain stage 70 functions as an integratorwhose time constant is set by resistors 52-53 and capacitor 55 to filterout switching transients present when switch 50 is opened and closed atthe frequency of clock signal CLOCK. This time constant preferably has avalue in the range of five times the period of CLOCK or greater. Forexample, if a period of CLOCK is ten microseconds, the time constant ofresistors 52-53 and capacitor 55 preferably is at least fiftymicroseconds. A control or threshold signal V_(TON) is provided at anode 74.

The operation of gain stage 70 is as follows. When COILON is high, suchas from time T1 to time T3 (I_(COIL) is nonzero), switch 50 is open.V_(err) functions as a reference voltage coupled to the non-invertinginput of amplifier 48. V_(TON) is coupled to the inverting input throughresistors 52 and 53 and the difference (V_(ERR)−V_(TON)) is integratedwith a time constant T_(SW0)=C₅₅*(R₅₂+R₅₃). When COILON is low, such asfrom time T3 to T4 (I_(COIL) is zero), switch 50 is closed and thevoltage across switch 50 is approximately zero. Substantially zero voltsis then applied to the inverting input of amplifier 48 through resistor52. V_(ERR) still acts as a reference voltage at the noninverting inputof amplifier 48, and the difference (V_(ERR)−0.0 volts) is integratedwith an integration time constant T_(SW1)=C₅₅*R₅₂. Resistor 53 isselected to be much smaller than resistor 52, so T_(SW0)=T_(SW1),approximately, to produce substantially equal integration time constantsregardless of the position of switch 50. Time constants T_(SW0) andT_(SW1) are preferably selected to be higher than the period of CLOCK,so a time-weighted average voltageV_(TON)*(T3−T1)/(T4−T1)=V_(TON)*D_(CYCLE) is present at the invertinginput of amplifier 48, where D_(CYCLE)=(T3−T1)/(T4−T1) is the duty cycleof I_(COIL) over a CLOCK period. The regulation of V_(OUT) by PFCcircuit 100 ensures that V_(ERR)=V_(TON)*D_(CYCLE) orV_(TON)=V_(ERR)/D_(CYCLE) at the respective inputs of amplifier 48.Since V_(ERR) is substantially constant over a period of CLOCK, so isthe product V_(TON)*D_(CYCLE), which results in I_(COIL) having asinusoidal shape and PFC circuit 100 having a high power factor.

V_(TIMING) is generated by charging a capacitance C₂₈ with a constantcurrent I_(TIMING), and therefore has a ramp shape that is a linearfunction of I_(TIMING). V_(TON) is coupled to an input of comparator 49to control the trip point at which timing voltage V_(TIMING) setstermination signal TERM to logic high to terminate charging currentI_(CH).

Note that I_(TIMING) is held substantially constant while correctionvoltage V_(ERR) is adjusted by COILON to generate threshold voltageV_(TON) so that the product T_(CH)*D_(CYCLE) is substantially constant.As indicated above, when T_(CH)*D_(CYCLE) is constant, the average valueof I_(COIL) is sinusoidal and in phase with AC line voltage VAC, whichresults in a high power factor. The high power factor is achieved whileswitching coil current I_(COIL) at a constant frequency with clocksignal CLOCK to reduce the level of electromagnetic interference or tofacilitate its attenuation by filtering.

FIG. 5 is a schematic diagram showing current modulator 14 in analternate embodiment. In this embodiment, correction voltage V_(ERR) iscoupled directly to the inverting input of comparator 49 to control theswitching threshold of V_(TIMING), while I_(TIMING) is adjusted by dutycycle DC of I_(COIL) to maintain the product T_(CH)*D_(CYCLE) constant.

Amplifier 60 operates as an integrator with integration time constantT_(SW)=C₆₁*R₆₈, where C₆₁ is the capacitance of capacitor 61 and R₆₈ isthe resistance of resistor 68. Capacitor 61 and resistor 68 preferablyare selected so that T_(sw) is much greater than the period of CLOCK.

From T1 to T3, when I_(COIL) is nonzero, COILON is high, switch 50 isopen and reference current I_(REF1) is routed through a resistor 66 todevelop a voltage V₆₆=I_(REF1)*R₆₆ on a node 77, where R₆₆ is theresistance of resistor 66. From T3 to T4, when I_(COIL) is zero, COILONis low, switch 50 is closed, and voltage V₆₆₌0.0 volts on node 77. Whenintegrated over a period of CLOCK, the time weighted average value ofvoltage V₆₆ is I_(REF1)*R₆₆*D_(CYCLE)=V₆₆*D_(CYCLE).

The output of amplifier 60 controls the base current of a transistor 65in conjunction with a resistor 69. This arrangement produces a collectorcurrent I₆₅ which is subtracted from a reference current I_(REF2) toproduce a current I_(OUT) that develops a voltage V₆₇ across resistor67. Collector current I₆₅ provides a feedback path that maintains V₆₆and V₆₇ at the same effective average potential, soI_(OUT)=I_(REF1)*D_(CYCLE)*R₆₆/R₆₇. Timing current I_(TIMING) ismirrored to I_(OUT) and scaled to a factor K by a current mirror 63, sothat I_(TIMING)=K*I_(OUT)=K*I_(REF1)*D_(CYCLE)*R₆₆/R₆₇. Hence,I_(TIMING) is proportional to duty cycle D_(CYCLE).

I_(TIMING) charges capacitor 28 as described above to produce timingvoltage V_(TIMING) as a ramp which is compared to V_(ERR) in comparator49 to produce control signal TEMP. Since I_(TIMING) is substantiallyconstant over a period of V_(IN) andV_(TIMING)=I_(TIMING)*T_(CH)=K*I_(REF1)*D_(CYCLE)*T_(CH)*R₆₆/R₆₇, theproduct T_(CH)*D_(CYCLE)is substantially constant. Therefore, I_(COIL)has an average current that is sinusoidal and PFC circuit 100 has a highpower factor.

In summary, the present invention provides a PFC circuit that is capableof operating at a constant or nearly constant frequency, therebyfacilitating the reduction of electromagnetic interference throughfiltering. A latch has an output that initiates a coil current inresponse to a transition edge of a clock signal to generate a PFCsignal. A current modulation circuit senses the PFC signal to establisha charging time of the coil current, and senses the coil current toestablish a duty cycle of the coil current over a period of the clocksignal. An output of the current modulation circuit is applied to aninput of the latch to provide a control signal that is a function of thecharging time and the duty cycle.

1. A power factor correction circuit, comprising: a first latch havingan output for initiating a coil current in response to a transition edgeof a clock signal to generate a PFC signal, and an input for receiving acontrol signal; a current modulation circuit having a first inputcoupled for receiving the PFC signal to establish a charging time of thecoil current, a second input coupled for sensing the coil current toestablish a duty cycle of the coil current over a period of the clocksignal, and an output for providing the control signal as a function ofthe charging time and the duty cycle; and a current sensor having aninput coupled for sensing the coil current and an output for providing asense signal, the current sensor including a first amplifier having afirst input coupled to the input of the current sensor and a secondinput for establishing a threshold level of the coil current, and thecurrent sensor also including a second latch having a first inputcoupled to the output of the first latch, a second input coupled to anoutput of the first amplifier and an output coupled to the second inputof the current modulation circuit for generating the sense signal as afirst logic state on the transition edge of the clock signal and as asecond logic state when the coil current falls below the thresholdlevel.
 2. The PFC circuit of claim 1, wherein the current modulationcircuit includes: a second amplifier having a first input for receivingthe PFC signal and a second input for receiving a reference signal; anda third amplifier having a first input coupled to an output of thesecond amplifier and an output for providing the control signal.
 3. ThePFC circuit of claim 2, wherein the current modulation circuit furtherincludes a first switch operating in response to a sense signal appliedat the second input of the current modulation circuit switching a secondinput of the third amplifier from the output of the third amplifier to areference node to establish the duty cycle.
 4. The PPC circuit of claim3, wherein the current modulation circuit further comprises a reactivecomponent coupled for averaging a potential at the output of the secondamplifier to produce the control signal.
 5. The PFC circuit of claim 4,wherein the reactive component is a capacitor that sets a time constantof the current modulation circuit to a value greater than the period ofthe clock signal.
 6. The PFC circuit of claim 3, wherein the current,modulation circuit further includes: a comparator having a first inputcoupled to an output of the second amplifier and an output for providingthe control signal; a current source coupled to a second input of thecomparator for charging a capacitance; and a second switch coupled tothe current source and responsive to the output of the first latch fordischarging the capacitance to terminate the charging portion of thecoil current.
 7. The PFC circuit of claim 1, wherein the currentmodulation circuit includes: a comparator having a first input coupledfor receiving a ramp signal and an output for providing the controlsignal; a second amplifier having a first input for receiving the PFCsignal, a second input for receiving a reference signal, and an outputcoupled to a second input of the comparator; and an averaging circuithaving an input coupled to the output of the second latch for averaginga first reference current over the period of the clock signal to producean averaging current indicative of the ditty cycle.
 8. The PPC circuitof claim 7, wherein the averaging circuit includes: a switch forswitching the first reference signal with the sense signal to produce aduty cycle signal; and an integrator having a first input coupled forreceiving the second reference signal, a second input for receiving theduty cycle signal, and an output for providing the averaging current. 9.The PFC Circuit of claim 8, wherein the averaging current is forcharging a capacitance to produce the ramp signal.
 10. A method ofcorrecting a power factor, comprising the steps of: initiating a coilcurrent at the beginning of a clock period to generate a power factorcorrected signal; sensing both a charging portion of the coil currentand a discharging portion of the coil current to determine a duty cycleof the coil current over the clock period; and terminating a chargingportion of the coil current with a control signal that is a function ofthe PFC signal and the duty cycle.
 11. The method of claim 10, whereinthe step of terminating includes the steps of: amplifying a differencebetween the PFC signal and a first reference signal to produce acorrection signal; and dividing the correction signal by the duty cycleto produce the control signal.
 12. The method of claim 11, wherein thestep of dividing includes the steps of: routing the correction signal toa first input of an amplifier; switching a second input of the amplifierto an output of the amplifier while the coil current flows; andswitching the second input of the amplifier to a reference node when thecoil current terminates.
 13. The PFC circuit of claim 12, wherein thestep of dividing further includes the step of filtering the controlsignal with a time constant greater than the clock period.
 14. Themethod circuit of claim 10, wherein the step of terminating includes thesteps of: charging a capacitance with a reference current at thebeginning of the clock period to generate a ramp signal; and comparingthe control signal with the ramp signal to produce a termination signalthat initiates a discharging portion of the coil current.
 15. The methodof claim 10, further comprising the steps of: dividing a referencecurrent by the duty cycle to produce a ramp current; charging acapacitance with the ramp current to produce a ramp voltage; andcomparing the ramp voltage with a reference signal to produce thetermination signal.
 16. An integrated power factor correction circuit,comprising: a driver circuit having a first input for receiving clockpulses to initiate a coil current, a second input for receiving acontrol signal to terminate a charging portion of the coil current, andan output for generating a PFC signal with the coil current; and amodulation circuit having a first input coupled for sensing the PFCsignal to set an amplitude of the coil current, a second input formonitoring the coil current over a period of the clock pulses to producea duty cycle signal, and an output for providing the control signal as afunction of the amplitude and the duty cycle signal.
 17. The integratedPFC circuit of claim 16, wherein the modulation circuit includes: anaveraging circuit having a first input coupled for sensing the PFCsignal, and an output for producing the control signal; and a switchoperating in response to the duty cycle signal for switching a secondinput of the averaging circuit between the output of the averagingcircuit and a reference signal.
 18. The integrated PFC signal of claim17, wherein the modulation circuit includes an error amplifier having afirst input coupled for receiving the PFC signal, a second input coupledfor receiving a reference signal, and an output coupled to the firstinput of the averaging circuit.
 19. The method of claim 10, whereinsensing both the charging portion of the coil current and thedischarging portion of the coil currenL to deternu.ne the duty cycle ofthe coil current over the clock period includes determining the dutycycle of the coil current as a portion of the clock period during whichboth the charging portion of the coil current and the dischargingportion of the coil current are substantially nonzero.